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lt1722/lt1723/lt1724 1 172234fb typical application features description single, dual, quad 200mhz low noise precision op amps the lt ? 1722/lt1723/lt1724 are single/dual/quad, low noise, low power, high speed operational ampli? ers. these products feature lower input offset voltage, lower input bias current and higher dc gain than devices with comparable bandwidth. the 200mhz gain bandwidth ensures high open-loop gain at video frequencies. the low input noise voltage is achieved with reduced supply current. the total noise is optimized for a source resistance between 0.8k and 12k. due to the input bias current cancellation technique used, the resistance seen by each input does not need to be balanced. the output drives a 150 load to 3v with 5v supplies. on a single 5v supply the output swings from 1.5v to 3.5v with a 500 load connected to 2.5v. the ampli? er is unity-gain stable (c load 100pf). the lt1722/lt1723/lt1724 are manufactured on linear technologys advanced low voltage complementary bipolar process. the lt1722 is available in the so-8 and 5-pin sot-23 packages. the lt1723 is available in the so-8 and ms8 packages. the lt1724 is available in the 14-lead so package. differential video line driver applications n 3.8nv/ hz input noise voltage n 3.7ma supply current n 200mhz gain bandwidth n low total harmonic distortion: C 85dbc at 1mhz n 70v/s slew rate n 400v maximum input offset voltage n 300na maximum input bias current n unity-gain stable n capacitive load stable up to 100pf n 23ma minimum output current n speci? ed at 5v and single 5v n low pro? le (1mm) sot-23 (thinsot ? ) package n video and rf ampli? cation n adsl, hdsl ii, vdsl receivers n active filters n wideband ampli? ers n buffers n data acquisition systems l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. line driver mulitburst video signal C + 1/2 lt1723 r5 2k r3 750 r7 62.5 +v out v in /2 62.5 load 62.5 load Cv in /2 Cv in 1723 ta01 v in Cv out 125 cat-5 twisted pair c1 5pf C + 1/2 lt1723 r4 2k v in 75 source r2 2k r1 75 r6 62.5 c2 5pf +v out 0.5v/div Cv out 0.5v/div v in 1v/div 1723 ta02
lt1722/lt1723/lt1724 2 172234fb pin configuration absolute maximum ratings total supply voltage (v + to v C ) ............................. 12.6v input voltage ............................................................. v s differential input voltage (note 2) .........................0.7v input current (note 2) .......................................... 10ma output short-circuit duration (note 3) ............ inde? nite (note 1) lt1722 top view nc v + out nc nc Cin +in v C s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + C t jmax = 150c, ja = 150c/w lt1722 out 1 v C 2 top view s5 package 5-lead plastic tsot-23 +in 3 5 v + 4 Cin +C t jmax = 150c, ja = 250c/w lt1723 top view v + out b Cin b +in b out a Cin a +in a v C s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 a b t jmax = 150c, ja = 190c/w lt1723 1 2 3 4 out a Cin a +in a v C 8 7 6 5 v + out b Cin b +in b top view ms8 package 8-lead plastic msop a b t jmax = 150c, ja = 250c/w lt1724 top view s package 14-lead plastic so 1 2 3 4 5 6 7 14 13 12 11 10 8 8 out a Cin a +in a v + +in b Cin b out b out d Cin d +in d v C +in c Cin c out c + C + C ad + C + C bc t jmax = 150c, ja = 100c/w operating temperature range (note 4) ...C40c to 85c speci? ed temperature range (note 5) ....C40c to 85c maximum junction temperature .......................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c
lt1722/lt1723/lt1724 3 172234fb order information lead free finish tape and reel part marking* package description specified temperature range lt1722cs8#pbf lt1722cs8#trpbf 1722 8-lead plastic so 0c to 70c lt1722is8#pbf lt1722is8#trpbf 1722i 8-lead plastic so ?40c to 85c lt1722cs5#pbf lt1722cs5#trpbf ltzb 5-lead plastic tsot-23 0c to 70c lt1722is5#pbf lt1722is5#trpbf ltzb 5-lead plastic tsot-23 ?40c to 85c lt1723cs8#pbf lt1723cs8#trpbf 1723 8-lead plastic so 0c to 70c lt1723is8#pbf lt1723is8#trpbf 1723i 8-lead plastic so ?40c to 85c lt1723cms8#pbf lt1723cms8#trpbf ltyc 8-lead plastic msop 0c to 70c lt1723ims8#pbf lt1723ims8#trpbf ltza 8-lead plastic msop ?40c to 85c lt1724cs#pbf lt1724cs#trpbf lt1724cs 14-lead plastic so 0c to 70c lt1724is#pbf lt1724is#trpbf lt1724is 14-lead plastic so ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
lt1722/lt1723/lt1724 4 172234fb electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 6) lt1722 sot-23 and lt1723 ms8 100 150 400 650 v v i os input offset current 40 300 na i b input bias current 40 300 na e n input noise voltage f = 10khz 3.8 nv/ hz i n input noise current f = 10khz 1.2 pa/ hz r in input resistance v cm = 3.5v differential 535 50 m k c in input capacitance 2pf input voltage range + input voltage range ? 3.5 4 C4 C3.5 v v cmrr common mode rejection ratio v cm = 3.5v 80 100 db psrr power supply rejection ratio v s = 2.3v to 5.5v 78 90 db a vol large-signal voltage gain v out = 3v, r l = 500 v out = 3v, r l = 150 10 7 17 14 v/mv v/mv v out output swing r l = 500, v in = 10mv r l = 150 , v in = 10mv 3.2 3.1 3.8 3.4 v v i out output current v out = 3v, 10mv overdrive 23 50 ma i sc short-circuit current v out = 0v, v in = 1v 35 90 ma sr slew rate a v = C1, (note 7) 45 70 v/s full power bandwidth 3v peak, (note 8) 3.7 mhz gbw gain bandwidth f = 200khz 115 200 mhz t s settling time a v = C1, 2v, 0.1% a v = C1, 2v, 0.01% 91 112 ns ns t r , t f rise time, fall time a v = 1, 10% to 90%, v in = 0.2v p-p , r l = 150 6 ns overshoot a v = 1, v in = 0.2v p-p , r l = 150, r f = 0 15 % propagation delay 50% v in to 50% v out = 0.2v p-p , r l = 150 3 ns r o output resistance a v = 1, f = 1mhz 0.15 channel separation v out = 3v, r l = 150 82 90 db i s supply current per ampli? er 3.7 4.5 ma t a = 25c. v s = 5v, v cm = 2.5v, r l to 2.5v, unless otherwise noted. v os input offset voltage (note 6) lt1722 sot-23 and lt1723 ms8 250 350 550 800 v v i os input offset current 20 300 na i b input bias current 20 300 na e n input noise voltage f = 10khz 4 nv/ hz i n input noise current f = 10khz 1.1 pa/ hz r in input resistance v cm = 1.5v to 3.5v differential 532 55 m k c in input capacitance 2pf input voltage range + input voltage range C 3.5 4 1 1.5 v v t a = 25c, v s = 5v, v cm = 0v, unless otherwise noted.
lt1722/lt1723/lt1724 5 172234fb electrical characteristics t a = 25c. v s = 5v, v cm = 2.5v, r l to 2.5v, unless otherwise noted. symbol parameter conditions min typ max units cmrr common mode rejection ratio v cm = 1.5v to 3.5v 80 100 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 4 10 v/mv v out output swing+ output swingC r l = 500, v in = 10mv r l = 500, v in = 10mv 3.6 3.8 0.9 1.4 v v i out output current v out = 3.5v or 1.5v, 10mv overdrive 10 20 ma i sc short-circuit current v out = 2.5v, v in = 1v 22 55 ma sr slew rate a v = C1, (note 7) 40 70 v/s full power bandwidth 1v peak, (note 8) 8.7 mhz gbw gain bandwidth (note 10) f = 200khz 115 180 mhz t r , t f rise time, fall time a v = 1, 10% to 90%, v in = 0.2v p-p , r l = 500 5 ns overshoot a v = 1, v in = 0.2v p-p , r l = 500 16 % propagation delay 50% v in to 50% v out , 0.1v, r l = 500 3 ns r o output resistance a v = 1, f = 1mhz 0.19 channel separation v out = 1.5v to 3.5v, r l = 500 82 90 db i s supply current per ampli? er 3.8 5 ma the denotes the speci? cations which apply over the temperature range of 0c t a 70c. v s = 5v, v cm = 0v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage (note 6) lt1722 sot-23 and lt1723 ms8 l l 700 850 v v input v os drift (note 9) l 37v/c i os input offset current l 350 na i b input bias current l 350 na input voltage range + input voltage range C l l 3.5 C3.5 v v cmrr common mode rejection ratio v cm = 3.5v l 75 db psrr power supply rejection ratio v s = 2.3v to 5.5v l 76 db a vol large-signal voltage gain v out = 3v, r l = 500 v out = 3v, r l = 150 l l 9 6 v/mv v/mv v out output swing r l = 500, v in = 10mv r l = 150, v in = 10mv l l 3.15 3.05 v v i out output current v out = 3v, 10mv overdrive l 22 ma i sc short-circuit current v out = 0v, v in = 1v l 30 ma sr slew rate a v = C1, (note 7) l 35 v/s gbw gain bandwidth f = 200khz l 100 mhz channel separation v out = 3v, r l = 150 l 81 db i s supply current per ampli? er l 5.45 ma
lt1722/lt1723/lt1724 6 172234fb electrical characteristics the l denotes the speci? cations which apply over the temperature range of 0c t a 70c. v s = 5v, v cm = 2.5v, r l to 2.5v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage (note 6) lt1722 sot-23 and lt1723 ms8 l l 850 950 v v input v os drift (note 9) l 37v/c i os input offset current l 350 na i b input bias current l 350 na input voltage range + input voltage range C l l 3.5 1.5 v v cmrr common mode rejection ratio v cm = 1.5v to 3.5v l 75 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 l 3 v/mv v out output swing+ output swingC r l = 500, v in = 10mv r l = 500, v in = 10mv l l 3.55 1.45 v v i out output current v out = 3.5v, or 1.5v, 10mv overdrive l 9ma i sc short-circuit current v out = 2.5v, v in = 1v l 11 ma sr slew rate a v = C1, (note 7) l 30 v/s gbw gain bandwidth (note 10) f = 200khz l 100 mhz channel separation v out = 1.5v to 3.5v, r l = 500 l 81 db i s supply current l 5.95 ma the l denotes the speci? cations which apply over the temperature range of C40c t a 85c. v s = 5v, v cm = 0v, unless otherwise noted. (note 5) symbol parameter conditions min typ max units v os input offset voltage (note 6) lt1722 sot-23 and lt1723 ms8 l l 900 1100 v v input v os drift (note 9) l 3 10 v/c i os input offset current l 400 na i b input bias current l 400 na input voltage range + input voltage range C l l 3.5 C3.5 v v cmrr common mode rejection ratio v cm = 3.5v l 75 db psrr power supply rejection ratio v s = 2.0v to 5.5v l 75 db a vol large-signal voltage gain v out = 3v, r l = 500 v out = 3v, r l = 150 l l 8 5 v/mv v/mv v out output swing r l = 500, v in = 10mv r l = 150, v in = 10mv l l 3.1 3.0 v v i out output current v out = 3v, 10mv overdrive l 20 ma i sc short-circuit current v out = 0v, v in = 1v l 25 ma sr slew rate a v = C1, (note 7) l 25 v/s gbw gain bandwidth f = 200khz l 90 mhz channel separation v out = 3v, r l = 150 l 80 db i s supply current l 5.95 ma
lt1722/lt1723/lt1724 7 172234fb electrical characteristics the denotes the speci? cations which apply over the temperature range of C40c t a 85c. v s = 5v, v cm = 2.5v, r l to 2.5v, unless otherwise noted. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by back-to-back diodes. if the differential input voltage exceeds 0.7v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 4: the lt1722c/lt1722i, lt1723c/lt1723i, lt1724c/lt1724i are guaranteed functional over the operating temperature range of ?40c to 85c. note 5: the lt1722c/lt1723c/lt1724c are guaranteed to meet speci? ed performance from 0c to 70c. the lt1722c/lt1723c/lt1724c are symbol parameter conditions min typ max units v os input offset voltage (note 6) lt1722 sot-23 and lt1723 ms8 l l 1000 1200 v v input v os drift (note 9) l 310v/c i os input offset current l 400 na i b input bias current l 400 na input voltage range + input voltage range C l l 3.5 1.5 v v cmrr common mode rejection ratio v cm = 1.5v to 3.5v l 75 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 l 2 v/mv v out output swing+ output swing? r l = 500 , v in = 10mv r l = 500 , v in = 10mv l l 3.5 1.5 v v i out output current v out = 3.5v or 1.5v, 30mv overdrive l 8ma i sc short-circuit current v out = 2.5v, v in = 1v l 10 ma sr slew rate a v = C1, (note 7) l 20 v/s gbw gain bandwidth (note 10) f = 200khz l 90 mhz channel separation v out = 1.5v to 3.5v, r l = 500 l 80 db i s supply current l 6.45 ma designed, characterized and expected to meet speci? ed performance from ?40c to 85c but are not tested or qa sampled at these temperatures. the lt1722i/lt1723i/lt1724i are guaranteed to meet speci? ed performance from ?40c to 85c. note 6: input offset voltage is pulse tested and is exclusive of warm-up drift. note 7: slew rate is measured between 2v on the output with 3v input for 5v supplies and 1v on the output with 1.5v input for single 5v supply. (for 5v supply, the voltage levels are 2.5v referred.) note 8: full power bandwidth is calculated from the slew rate: fpbw = sr/2 v p note 9 : this parameter is not 100% tested. note 10 : this parameter is guaranteed through correlation with slew rate.
lt1722/lt1723/lt1724 8 172234fb typical performance characteristics input bias current vs temperature input noise spectral density open-loop gain vs resistive load total noise vs unmatched source resistance warm-up drift vs time v os shift vs v cm and v s supply current vs temperature input common mode range vs supply voltage input bias current vs common mode voltage temperature (c) C50 supply current (ma) 4.0 4.5 5.0 25 75 1723 g01 3.5 3.0 C25 0 50 100 125 2.5 2.0 per amplifier v s = 5v v s = 5v supply voltage (v) 0 input common mode range (v) 2 4 5 1723 g02 13 6 7 0.5 v + C0.5 C1.0 C1.5 C1.2 2.0 1.5 1.0 0.5 v C (v os ) < 500v t a = 25c input common mode voltage (v) C5 input bias current (na) 400 300 200 100 0 C100 C200 C300 C400 3 1723 g03 C3 C1 1 5 2 C4 C2 0 4 v s = 5v t a = C45c t a = 125c t a = 25c t a = 85c temperature (c) C50 input bias current (na) 20 40 60 25 75 1723 g04 0 C20 C25 0 50 i b C i b C i b + i b + 100 125 C40 C60 v s = 5v v s = 5v frequency (khz) 0.01 0.1 1 10 100 0.1 1 10 i n 1 10 100 1723 g05 input voltage noise (nv/ hz ) input current noise (pa/ hz ) e n load resistance () 100 74.0 open-loop gain (db) 76.5 79.0 81.5 84.0 89.0 1000 10000 1723 g06 86.5 t a = 25c v s = 5v, v o = 3v v s = 2.5v, v o = 1v source resistance, r s (k) 1 total noise voltage (nv/ hz ) 10 0.01 1 10 100 1723 g07 0.1 0.1 100 v s = 5v t a = 25c f = 10khz total noise resistor noise + C r s time after power-up (sec) 0 offset voltage drift (v) 10 20 30 5 15 25 20 40 60 80 1723 g08 100 10 030507090 lt1722s8 t a = 25c typical data v s = 5v v s = 2.5v common mode voltage (v) C300 v os shift (v) C100 100 300 C200 0 200 C3 C1 1 3 1723 g09 5 C4 C5 C2 0 2 4 v s = 6.3v v s = 5v v s = 4v v s = 3v v s = 2.5v t a = 25c typical part v s = 6v
lt1722/lt1723/lt1724 9 172234fb typical performance characteristics open-loop gain vs temperature output voltage swing vs supply voltage output short-circuit current vs temperature gain and phase vs frequency overshoot vs capacitive load output impedance vs frequency v os vs temperature undistorted output swing vs frequency undistorted output swing vs frequency temperature (c) C60 C500 offset voltage (v) C400 C200 C100 0 60 80 100 200 1723 g10 C300 C40 C20 0 20 40 120 100 v s = 5v typical part v s = 2.5v frequency (mhz) 0.1 0 output voltage (v p-p ) 2 4 6 8 110 1723 g11 10 1 3 5 7 9 a v = 1, r f = 0, r in = 500 a v = C1, r f = 500 v s = 5v r l = 150 2% max distortion frequency (mhz) 0.1 0 output voltage (v p-p ) 1.0 2.0 3.0 4.0 110 1723 g12 5.0 0.5 1.5 2.5 3.5 4.5 a v = C1, r f = 500 v s = 5v r l = 500 2% max distortion a v = 1, r f = 0, r in = 500 temperature (c) C50 86 open-loop gain (db) 76 78 79 80 85 82 0 50 75 1723 g13 77 83 84 81 C25 25 100 125 v s = 5v, v o = 3v v s = 5v, v o = 1v r l = 500 r l = 500 r l = 150 supply voltage (v) 2.0 output voltage swing (v) 2.5 3.5 3.0 4.0 5.0 4.5 1723 g08 5.5 v+ C0.5 C1.0 C1.5 C2.0 2.0 1.5 1.0 0.5 v C 6.0 t a = 25c v in = 10mv r l = 500 r l = 500 r l = 150 r l = 150 temperature (c) C50 60 output short-circiut current (ma) 65 75 80 85 110 95 0 50 75 1723 g15 70 100 105 90 C25 25 100 125 v s = 5v v s = 5v source source sink sink frequency (mhz) 20 gain (db) phase (deg) 80 90 10 0 70 40 60 50 30 0.01 1 10 100 1723 g16 C10 20 80 90 10 0 70 40 60 50 30 C10 0.1 phase gain 5v 5v 5v 5v t a = 25c a v = C1 r f = r g = 500 capacitive load (pf) 10 overshoot (%) 50 60 70 80 50 1723 g17 40 30 45 55 65 75 35 25 20 20 30 40 60 70 80 90 100 v s = 5v r l = 500 v in = 2v p-p f = 1mhz a v = C1, r f = 500, r s = 0 a v = 1, r f = 0, r s = 500 a v = 1, r f = 500, r s = 0 frequency (mhz) 0.01 0.001 output impedance () 0.1 100 110 0.1 100 1723 g18 0.01 1 10 t a = 25c v s = 5v a v = 100 a v = 10 a v = 1
lt1722/lt1723/lt1724 10 172234fb typical performance characteristics channel separation vs frequency power supply rejection ratio vs frequency common mode rejection ratio vs frequency slew rate vs temperature phase margin vs supply voltage gain bandwidth vs supply voltage gain vs frequency, a v = 1 gain vs frequency, a v = 1 gain vs frequency, a v = C1 frequency (mhz) 1 C1 gain (db) 1 3 5 7 10 100 1723 g19 0 2 4 6 8 9 t a = 25c a v = 1 r f = 0 no r l 5v 5v c l = 100pf c l = 50pf c l = 0pf frequency (mhz) 1 C1 gain (db) 1 3 5 7 10 100 1723 g20 0 2 4 6 8 9 t a = 25c a v = 1 no r l no c l 5v 5v r f = 500 r f = 1k r f = 0 frequency (mhz) 1 C1 gain (db) 1 3 5 7 10 100 1723 g21 0 2 4 6 8 9 t a = 25c a v = C1 r f = r g = 500 no r l 5v 5v c l = 100pf c l = 50pf c l = 0pf frequency (mhz) 0.1 C50 crosstalk (db) C30 C10 1 10 100 1723 g22 C70 C60 C40 C20 C80 C90 t a = 25c v o = 6v p-p r l = 150 frequency (mhz) 40 power supply rejection ratio (db) 100 30 20 90 60 80 70 50 0.01 1 10 100 1723 g23 10 0 0.1 t a = 25c v s = 5v a v = 1 Cpsrr +psrr frequency (mhz) 40 common mode rejection ratio (db) 100 110 30 20 90 60 80 70 50 0.01 1 10 100 1723 g24 10 0.1 t a = 25c v s = 5v temperature (c) C50 slew rate (v/s) 90 25 1723 g40 60 40 C25 0 50 30 20 100 80 70 50 75 100 125 t a = 25c a v = C1 r g = r f = 500 v s = 5v, sr + v s = 5v, sr C v s = 2.5v, sr C v s = 2.5v, sr + supply voltage (v) 2.5 35 phase margin (deg) 40 50 55 60 4.5 80 1723 g41 45 3.5 3 5 5.5 46 65 70 75 t a = 25c a v = C1 v in = C20dbm r g = r f = 500 r l = 500 c l = 5pf c l = 25pf c l = 55pf r l = 500 r l = 500 r l = 150 r l = 150 r l = 150 supply voltage (v) 2.5 gain bandwidth (mhz) 215 4 1723 g42 200 190 3 3.5 4.5 185 180 220 210 205 195 5 5.5 6 t a = 25c a v = C1 v in = C20dbm r g = r f = 500 c l = 25pf c l = 25pf r l = 150 r l = 500 c l = 5pf c l = 5pf c l = 55pf c l = 55pf
lt1722/lt1723/lt1724 11 172234fb typical performance characteristics harmonic distortion vs frequency a v = 2, v o = 0.2v p-p harmonic distortion vs frequency a v = 2, v o = 0.2v p-p harmonic distortion vs frequency a v = 1, v o = 2v p-p harmonic distortion vs frequency a v = 1, v o = 2v p-p harmonic distortion vs frequency a v = 2, v o = 2v p-p slew rate vs supply voltage harmonic distortion vs frequency a v = 1, v o = 0.2v p-p harmonic distortion vs frequency a v = 1, v o = 0.2v p-p supply voltage (v) 2 50 slew rate (v/s) 55 65 70 sr + sr + sr C sr C 75 3 4 4.5 6.5 1723 g25 60 2.5 3.5 5 5.5 6 80 v in_p-p = v s , v out_mes at 2/3 of v in_p-p v in = 1.5v, v out_mes at 1v t a = 25c a v = C1 r f = r g = r l = 500 frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g26 C50 v s = 5v a v = 1 r f = 0 r in = 0 v o = 0.2v p-p r l = 150, 2nd r l = 500, 2nd r l = 500, 3rd r l = 150, 3rd frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g27 C50 v s = 5v a v = 1 r f = 0 r in = 0 v o = 0.2v p-p r l = 150, 2nd r l = 500, 2nd r l = 150, 3rd r l = 500, 3rd frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g28 C50 v s = 5v a v = 2 r f = 500 v o = 0.2v p-p r l = 150, 2nd r l = 150, 3rd r l = 500, 2nd r l = 500, 3rd frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g29 C50 v s = 5v a v = 2 r f = 500 v o = 0.2v p-p r l = 150, 2nd r l = 150, 3rd r l = 500, 2nd r l = 500, 3rd frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g30 C50 v s = 5v a v = 1 r f = 0 r in = 500 v o = 2v p-p r l = 150, 3rd r l = 500, 3rd r l = 150, 2nd r l = 500, 2nd frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g31 C50 v s = 5v a v = 1 r f = 0 r in = 500 v o = 2v p-p r l = 150, 3rd r l = 500, 3rd r l = 150, 2nd r l = 500, 2nd frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g32 C50 v s = 5v a v = 2 r f = 500 v o = 2v p-p r l = 150, 3rd r l = 500, 3rd r l = 500, 2nd r l = 150, 2nd
lt1722/lt1723/lt1724 12 172234fb typical performance characteristics large-signal transient, a v = 1 small-signal transient, a v = 1 small-signal transient, a v = 1 large-signal transient, a v = C1 small-signal transient, a v = C1 harmonic distortion vs frequency a v = 2, v o = 2v p-p settling time vs output step frequency (mhz) 0.1 C100 harmonic distortion (dbc) C90 C80 C70 C60 C40 110 1723 g33 C50 v s = 5v a v = 2 r f = 500 v o = 2v p-p r l = 150, 3rd r l = 500, 3rd r l = 500, 2nd r l = 150, 2nd settling time (ns) 60 output step (v) 0 1.5 2.0 140 1723 g43 C0.5 C1.0 C3.0 80 100 120 70 90 110 130 C2.0 3.0 2.5 1.0 0.5 C1.5 C2.5 v s = 5v a v = C1 r f = 500 c f = 0pf 0.1% settling 0.1% settling 0.01% settling 0.01% settling small-signal transient, a v = C1 1v/div a v = 1 r s = 500 r f = 0 50ns/div 1723 g34 50mv/div a v = 1 r s = 0 r f = 0 c l = 0pf 50ns/div 1723 g35 50mv/div a v = 1 r s = 0 r f = 0 c l = 100pf 50ns/div 1723 g36 1v/div a v = C1 r g = 500 r f = 500 50ns/div 1723 g37 50mv/div a v = C1 r g = 500 r f = 500 c l = 0pf 50ns/div 1723 g38 50mv/div a v = C1 r g = 500 r f = 500 c l = 100pf 50ns/div 1723 g39
lt1722/lt1723/lt1724 13 172234fb the lt1722/lt1723/lt1724 may be inserted directly into many operational ampli? er applications improving both dc and ac performance, as well as noise and distortion. layout and passive components the lt1722/lt1723/lt1724 ampli? ers are more tolerant of less than ideal layouts than other high speed ampli? ers. for maximum performance (for example, fast settling time) use a ground plane, short lead lengths and rf quality bypass capacitors (0.01f to 0.1f). for high drive current applications, use low esr supply bypass capacitors (1f to 10f tantalum). the output/input parasitic coupling should be minimized when high frequency performance is required. the parallel combination of the feedback resistor and gain setting resistor on the inverting input combine with the input capacitance to form a pole that can cause peaking or even oscillations. in parallel with the feedback resistor, a capacitor of value: c f > r g ? c in /r f should be used to cancel the input pole and optimize dynamic performance. for unity-gain applications where a feedback resistor is used, such as an i-to-v converter, c f should be ? ve times greater than c in ; an optimum value for c f is 10pf. input considerations each of the lt1722/lt1723/lt1724 inputs is protected with back-to-back diodes across the bases of the npn input devices. if greater than 0.7v differential input voltages are anticipated, the input current must be limited to less than 10ma with an external series resistor. each input also has two esd clamp diodesone to each supply. if an input is driven beyond the supply, limit the current with an external resistor to less than 10ma. the input stage protection circuit is shown in figure 1. the input currents of the lt1722/lt1723/lt1724 are typically in the tens of na range due to the bias current cancellation technique used at the input. as the input offset current can be greater than either input current, applications information figure 1. input stage protection adding resistance to balance source resistance is not recommended. the value of the source resistor should be below 12k as it actually degrades dc accuracy and also increases noise. total input noise the total input noise of the lt1722/lt1723/lt1724 is optimized for a source resistance between 0.8k and 12k. within this range, the total input noise is dominated by the noise of the source resistance itself. when the source resistance is below 0.8k, voltage noise of the ampli? er dominates. when the source resistance is above 12k, the input noise current is the dominant contributor. capacitive loading the lt1722/lt1723/lt1724 drive capacitive loads up to 100pf with unity gain. as the capacitive load increases, both the bandwidth and the phase margin decrease causing peaking in the frequency response and overshoot in the transient response. when there is a need to drive a larger capacitive load, a 25 series resistance assures stability with any value of load capacitor. a feedback capacitor also helps to reduce any peaking. power dissipation the lt1722/lt1723/lt1724 combine high speed and large output drive in a small package. maximum junction temperature (t j ) is calculated from the ambient temperature (t a ), power dissipation per ampli? er (p d ) and number of ampli? ers (n) as follows: t j = t a + (n ? p d ? ja ) d1 d3 +in +in d4 d5 d6 1723 f01 d2 i 1 i 2 r q1 r ext q2 v s + v s C Cin Cin r ext
lt1722/lt1723/lt1724 14 172234fb simplified schematic applications information power dissipation is composed of two parts. the ? rst is due to the quiescent supply current and the second is due to on-chip dissipation caused by the load current. worst-case instantaneous power dissipation for a given resistive load in one ampli? er occurs at the maximum supply current and when the output voltage is at half of either supply voltage (or the maximum swing if less than half supply voltage). therefore p d(max) in one ampli? er is: p d(max) = (v + C v C )(i s(max) ) + (v + /2) 2 /r l or p d(max) = (v + C v C )(i s(max) ) + (v + C v o(max) )(v o(max) /r l ) example. worst-case conditions are: both op amps in the lt1723is8 are at t a = 85c, v s = 5v, r l = 150, v out = 2.5v. p d(max) = 2 ?[(10v)(5.95ma) + (2.5v) 2 /150] = 203mw t j(max) = 85c + (203mw)(190c/w) = 124c which is less than the absolute maximum rating at 150c. circuit operation the lt1722/lt1723/lt1724 circuit topology is a voltage feedback ampli? er. the operation of the circuit can be understood by referring to the simpli? ed schematic. the ? rst stage is a folded cascode formed by the transistors q1 through q4. a degeneration resistor, r, is used in the input stage. the current mirror q5, q6 is bootstrapped by q7. the capacitor, c, assures the bandwidth and the slew rate performance. the output stage is formed by complementary emitter followers, q8 through q11. the diodes d1 and d2 protect against input reversed biasing. the remaining part of the circuit assures optimum voltage and current biases for all stages. low noise, reduced current supply, high speed and dc accurate parameters are distinctive features of the lt1722/lt1723/lt1724 . q2 +in q1 d1 d2 r ?Cin r2 q6 q7 q9 q10 v s + v s C out 1723 ss q11 q8 q4 c v bias i 3 i 4 i 5 i 2 i 1 r1 q5 q3
lt1722/lt1723/lt1724 15 172234fb package description 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 typ 5 plcs (note 3) datum a 0.09 C 0.20 (note 3) s5 tsot-23 0302 rev b pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635)
lt1722/lt1723/lt1724 16 172234fb ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 C 6 typ detail a detail a gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 0C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) package description
lt1722/lt1723/lt1724 17 172234fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description s package 14-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) 1 n 2 3 4 .150 C .157 (3.810 C 3.988) note 3 14 13 .337 C .344 (8.560 C 8.738) note 3 .228 C .244 (5.791 C 6.197) 12 11 10 9 5 6 7 n/2 8 .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 0 C 8 typ .008 C .010 (0.203 C 0.254) s14 0502 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc .245 min n 1 2 3 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt1722/lt1723/lt1724 18 172234fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2002 lt 0909 rev b ? printed in usa related parts typical application part number description comments lt1677 single, low noise rail-to-rail ampli? er 3v operation, 2.5ma supply current, 4.5nv/ hz max e n , 60v max v os lt1800/lt1801/lt1802 single/dual/quad, low power, 80mhz rail-to-rail precision ampli? er 1.6ma supply current, 350v v os , 2.3v operation lt1806/lt1807 single/dual, low noise 325mhz rail-to-rail ampli? ers 2.5v operation, 550v max v os , 3.5nv/ hz lt1809/lt1810 single/dual, low distortion 180mhz rail-to-rail ampli? ers 2.5v operation, ?90dbc at 5mhz distortion lt1812/lt1813/lt1814 single/dual/quad, 3ma, 750v/s ampli? ers 5v operation, 3.6ma supply current, 40ma min output current lt6202/lt6203/lt6204 single/dual/quad, 100mhz, low noise rail-to-rail op amps 2nv/ hz , 2.5ma on single 3v supply 4- to 2-wire local echo cancellation differential receiver ampli? er n:1 ? ? (n = 1) v l 100 line 50 50 1k 1k v r line receiver 10pf 2k 1k 1k 2k 10pf 1723 ta03 r l n 2 C + C + C + C + v d line driver 1/2 lt1723 1/2 lt1723 1/2 lt1739 1/2 lt1739

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